Yuan Lu, Chief Verification Architect at Atrenta and inventor of Assertion Synthesis,
will present a tutorial at DVCon 2013 entitled: "Visibility into the Functional
Verification Process using Assertion Synthesis"
Yuan Lu - Atrenta Inc.
John Henri Jr. - Cadence Design Systems, Inc.
Baosheng Wang - Advanced Micro Devices, Inc.
Thursday, February 28, 2013
1:30PM - 5:00PM | DONNER BALLROOM
DVCon 2013, DoubleTree Hotel, San Jose, CA
This tutorial consists of an overview of Assertion Synthesis by its inventor,
along with use models and in-depth discussions of methodologies for Assertion
Synthesis deployment at different stages in the verification cycle. Cadence
Design Systems will participate, explaining how assertions, code and
functional coverage at the sub-system and system level can be used to
improve coverage closure and raise the level of design confidence prior
to tape-out. AMD will also participate and share their experiences using
assertions in areas such as performance modeling and emulation.
For more details visit http://dvcon.org/2013_event_details?id=144-8-T
Atrenta’s SpyGlass® Predictive Analysis software platform significantly
improves design efficiency for the world’s leading semiconductor and
consumer electronics companies. Patented solutions provide early design insight
into the demanding performance, power and area requirements of the complex
system on chips (SoCs) fueling today’s consumer electronics revolution.
More than two hundred companies and thousands of design engineers worldwide
rely on SpyGlass to reduce risk and cost before traditional EDA tools are
deployed. SpyGlass functions like an interactive guidance system for design
engineers and managers, finding the fastest and least expensive path to implementation
for complex SoCs.
SpyGlass from Atrenta: Insight. Efficiency. Confidence. www.atrenta.com
For more information, contact:
Tel: +1-408-453-3333; +91-9810313320
Liz Massingill (firstname.lastname@example.org)